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Espressif Systems /ESP32-C3 /EFUSE /RD_REPEAT_DATA0

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Interpret as RD_REPEAT_DATA0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RD_DIS0 (DIS_RTC_RAM_BOOT)DIS_RTC_RAM_BOOT 0 (DIS_ICACHE)DIS_ICACHE 0 (DIS_USB_JTAG)DIS_USB_JTAG 0 (DIS_DOWNLOAD_ICACHE)DIS_DOWNLOAD_ICACHE 0 (DIS_USB_DEVICE)DIS_USB_DEVICE 0 (DIS_FORCE_DOWNLOAD)DIS_FORCE_DOWNLOAD 0 (RPT4_RESERVED6)RPT4_RESERVED6 0 (DIS_CAN)DIS_CAN 0 (JTAG_SEL_ENABLE)JTAG_SEL_ENABLE 0SOFT_DIS_JTAG 0 (DIS_PAD_JTAG)DIS_PAD_JTAG 0 (DIS_DOWNLOAD_MANUAL_ENCRYPT)DIS_DOWNLOAD_MANUAL_ENCRYPT 0USB_DREFH 0USB_DREFL 0 (USB_EXCHG_PINS)USB_EXCHG_PINS 0 (VDD_SPI_AS_GPIO)VDD_SPI_AS_GPIO 0BTLC_GPIO_ENABLE 0 (POWERGLITCH_EN)POWERGLITCH_EN 0POWER_GLITCH_DSENSE

Description

BLOCK0 data register 1.

Fields

RD_DIS

Set this bit to disable reading from BlOCK4-10.
DIS_RTC_RAM_BOOT

Set this bit to disable boot from RTC RAM.
DIS_ICACHE

Set this bit to disable Icache.
DIS_USB_JTAG

Set this bit to disable function of usb switch to jtag in module of usb device.
DIS_DOWNLOAD_ICACHE

Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).
DIS_USB_DEVICE

Set this bit to disable usb device.
DIS_FORCE_DOWNLOAD

Set this bit to disable the function that forces chip into download mode.
RPT4_RESERVED6

Reserved (used for four backups method).
DIS_CAN

Set this bit to disable CAN function.
JTAG_SEL_ENABLE

Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
SOFT_DIS_JTAG

Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.
DIS_PAD_JTAG

Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
DIS_DOWNLOAD_MANUAL_ENCRYPT

Set this bit to disable flash encryption when in download boot modes.
USB_DREFH

Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.
USB_DREFL

Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.
USB_EXCHG_PINS

Set this bit to exchange USB D+ and D- pins.
VDD_SPI_AS_GPIO

Set this bit to vdd spi pin function as gpio.
BTLC_GPIO_ENABLE

Enable btlc gpio.
POWERGLITCH_EN

Set this bit to enable power glitch function.
POWER_GLITCH_DSENSE

Sample delay configuration of power glitch.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data